Powertech Technology Inc, a semiconductor assembly, testing, and packaging company based in Taiwan, has reportedly made plans to build an advanced packaging fab by investing NT$50 billion in the coming five years. The advanced fab would be aimed at creating next-generation packaging technology, to meet the rising demand for small size & energy saver chips to be employed in AI, IoT, and autonomous vehicles.
According to Powertech Technology, Fab 3 located in Hsinchu Science Park, would be the first fab in the world to commercially employ fan-out panel-level packaging (FOPLP) technology, once it starts operating. Apparently, Fab 3 would produce nearly 3,000 jobs, with an installed volume of fifty thousand sheets per month, or 150000 wafers of 12-inch, the company stated.
Sources claim that Powertech has made this announcement only after the firm’s major advances in commercializing this technology, since it started investing in it 2 years ago.
D.K. Tsai, Chairman of Powertech Technology Inc, was reportedly quoted stating that it has become extremely difficult and expensive to reduce transistor size to abide by Moore’s law. However, DigiTimes quotes Tsai to also be stating that FOPLP is now ideal to enforce heterogeneous integration packaging of ICs at reduced prices and indeed, will turn out to be a revolutionary packaging trend in the next ten years.
For the record, the FOPLP technology is highly cost-effective, in comparison to competing fan-out wafer-level packaging technology, as a rectangular panel can be divided into more chips than round wafers of 12-inches.
As per experts familiar with the knowledge of the matter, the world’s biggest chip testing and packaging firm, ASE Technology Holding Co. is also working on FOPLP technology, but no official announcement regarding this has been made so far.
As per Powertech, the Fab 3 plant would fulfill the escalating demand for innovative chip packaging technologies in the coming decade.